PHOTONIC INTEGRATED CIRCUITS WITH ALIGNED PHOTONIC DIES

原文（中文）

Various embodiments disclosed herein describe photonic integrated circuits having multiple photonic dies, and techniques for vertically aligning two photonic dies of a photonic integrated circuit. In some variations, a photonic die may include a cladding layer that is used to define a bottom surface of a waveguide layer. A portion of the cladding layer is used as an etch stop to define a top surface of a post, which may assist in vertically aligning the photonic die relative to an additional photonic die. Additionally or alternatively, a photonic die may include a ridge waveguide and multiple etch stop layers, of which a first etch stop layer defines a height of the ridge waveguide and a second etch stop layer defines a contact surface. The contact surface may contact a portion of an additional photonic die to help provide vertical alignment between the two photonic dies.