DATA LINK RECEIVER CALIBRATION
卷宗概要
发明人
Ravi SHIVNARAINE; Charles Walter BOECKER; Michael Raymond TROMBLEY; Eric Douglas GROEN; Simon S. LI; Shankar Srinivasa TANGIRALA
IPC 分类
CPC 分类
Systems and methods are disclosed for phase calibration between clock and data lanes at a data link receiver. In calibration mode, matching signals are transmitted over the clock and data lanes, and a phase offset is measured at the receiver. A phase shifter in one signal path is adjusted to a first phase to obtain a desired phase offset. For operation mode, the phase shifter is set based on the first phase. Embodiments measure phase offset using an XOR gate and use a phase interpolator as the phase shifter. Embodiments with multiple data lanes apply coarse calibration to a shared clock lane relative to a first data lane, and similar fine calibration to other data lanes. Calibration provides optimum signal-to-noise ratio or timing margin, enabling high transmission speeds at relatively low power. Variations are disclosed.
原文（中文）
Systems and methods are disclosed for phase calibration between clock and data lanes at a data link receiver. In calibration mode, matching signals are transmitted over the clock and data lanes, and a phase offset is measured at the receiver. A phase shifter in one signal path is adjusted to a first phase to obtain a desired phase offset. For operation mode, the phase shifter is set based on the first phase. Embodiments measure phase offset using an XOR gate and use a phase interpolator as the phase shifter. Embodiments with multiple data lanes apply coarse calibration to a shared clock lane relative to a first data lane, and similar fine calibration to other data lanes. Calibration provides optimum signal-to-noise ratio or timing margin, enabling high transmission speeds at relatively low power. Variations are disclosed.