ADDRESS TRANSLATION FOR ACCELERATOR-TRIGGERED MEMORY ACCESS REQUEST

原文（中文）

An apparatus comprises processing circuitry to execute instructions; memory management circuitry associated with the processing circuitry, to perform address translation in response to memory access instructions executed by the processing circuitry; and accelerator control interface circuitry to exchange control signals with at least one hardware accelerator configurable, based on instructions executed by the processing circuitry, to perform a delegated task. In response to an accelerator-triggered memory access request received at the accelerator control interface circuitry from a given hardware accelerator, the memory management circuitry associated with the processing circuitry is configured to translate a virtual address specified by the accelerator-triggered memory access request to a physical address of a memory system location to be accessed in response to the accelerator-triggered memory access request.