CACHE TECHNIQUES FOR MEMORY SYSTEM READ COMMANDS
卷宗概要
发明人
Deping He; Liang Yu; Caixia Yang
IPC 分类
CPC 分类
Methods, systems, and devices for cache techniques for memory system read commands are described. A memory device of a memory system may reduce latency associated with cache access operations based on receiving a multi-plane command from the memory system. For example, the memory system may transmit an access command that indicates (e.g., using one or more bits, via a prefix associated with the command) that an access operation is for a multi-plane read of the memory device. The memory device may transfer data from a first cache of the memory device to a second cache of the memory device prior to receiving each address indication for the access operation. As such, the memory device may concurrently perform the transfer of the data with the receiving of at least one address indication, thereby reducing latency associated with the access operation and response times of the memory system.
原文（中文）
Methods, systems, and devices for cache techniques for memory system read commands are described. A memory device of a memory system may reduce latency associated with cache access operations based on receiving a multi-plane command from the memory system. For example, the memory system may transmit an access command that indicates (e.g., using one or more bits, via a prefix associated with the command) that an access operation is for a multi-plane read of the memory device. The memory device may transfer data from a first cache of the memory device to a second cache of the memory device prior to receiving each address indication for the access operation. As such, the memory device may concurrently perform the transfer of the data with the receiving of at least one address indication, thereby reducing latency associated with the access operation and response times of the memory system.