Methods and Apparatus for Efficiently Processing Load Instruction Sequences
卷宗概要
发明人
Adithya RANGANATHAN; Rahul BERA; Joydeep RAKSHIT; Sujit MAHTO; Anant Vithal NORI; Jayesh GAUR; Sreenivas SUBRAMONEY
IPC 分类
CPC 分类
An apparatus and method for improving the efficiency of sequences of load instructions. For example, one embodiment of a method comprises: storing, in one or more tracking structures of a memory operations circuit, information related to executed instances of a load instruction, including a loaded data value, a physical address from which the loaded data value was accessed, and a flag to be set to a first value when new instances of the load instruction are to be excluded from execution; detecting a first instance of the load instruction when the flag is set to the first value; and responsively replacing the first instance of the load instruction with a move instruction which, when executed, is to move the loaded data value from a first register to a destination architectural register indicated by the new load instruction.
原文（中文）
An apparatus and method for improving the efficiency of sequences of load instructions. For example, one embodiment of a method comprises: storing, in one or more tracking structures of a memory operations circuit, information related to executed instances of a load instruction, including a loaded data value, a physical address from which the loaded data value was accessed, and a flag to be set to a first value when new instances of the load instruction are to be excluded from execution; detecting a first instance of the load instruction when the flag is set to the first value; and responsively replacing the first instance of the load instruction with a move instruction which, when executed, is to move the loaded data value from a first register to a destination architectural register indicated by the new load instruction.