PARTITIONED STORE QUEUE ENGINE IN A SEMICONDUCTOR SYSTEM
卷宗概要
发明人
Dushyanth BHOJARAJA; Paul Alan BEAZLEY
IPC 分类
CPC 分类
Methods, systems, and devices for providing partitioned store queue management using a partitioned store queue engine of a semiconductor system are described. Partitioned store queue management can refer to hardware-based techniques associated with a store queue architecture that helps managing memory operations, including storing of data to memory. Hardware-based techniques are employed to handle store instructions in a processor pipeline. In operation, a control store queue entry is allocated in a control store queue of a partitioned store queue when a store instruction is in a decode-dispatch stage. A data store queue entry is allocated when the store instruction in a memory stage of the processor pipeline. The data store queue is freed up when the data is ready in the data store queue entry. The control queue entry and data store queue entry is deallocated when the store instruction is in a write back stage of the processor pipeline.
原文（中文）
Methods, systems, and devices for providing partitioned store queue management using a partitioned store queue engine of a semiconductor system are described. Partitioned store queue management can refer to hardware-based techniques associated with a store queue architecture that helps managing memory operations, including storing of data to memory. Hardware-based techniques are employed to handle store instructions in a processor pipeline. In operation, a control store queue entry is allocated in a control store queue of a partitioned store queue when a store instruction is in a decode-dispatch stage. A data store queue entry is allocated when the store instruction in a memory stage of the processor pipeline. The data store queue is freed up when the data is ready in the data store queue entry. The control queue entry and data store queue entry is deallocated when the store instruction is in a write back stage of the processor pipeline.