HOST-FACING DMA FAILURE DETECTION FOR TRANSPORT OFFLOAD WITH MULTI-STAGE QUEUE OPERATIONS
卷宗概要
发明人
Xuyang WANG; Vishwas DANIVAS; Sanjay SHANBHOGUE; Murty Subbaramachandra KOTHA; Mehul Jitendrabhai VORA; Rohit Kailash SHARMA
IPC 分类
CPC 分类
Embodiments herein describe including one or more error indicating bits in a task pointer (e.g., a WQE) to tell a downstream queue or stage, such as a pipeline, that an upstream queue or stage detected a DMA error. The communication from each upstream stage or pipeline to the next is typically through posting WQEs into the next stage queue and ringing doorbells. The embodiments herein use one or more error indicator bits (e.g., color bits) in the WQE to inform a downstream queue (e.g., a downstream pipeline) that the upstream queue/pipeline detected a failed DMA operation. The downstream queue can then perform error handling where it reclaims the resources allocated for the WQE (such as an intermediate buffer).
原文（中文）
Embodiments herein describe including one or more error indicating bits in a task pointer (e.g., a WQE) to tell a downstream queue or stage, such as a pipeline, that an upstream queue or stage detected a DMA error. The communication from each upstream stage or pipeline to the next is typically through posting WQEs into the next stage queue and ringing doorbells. The embodiments herein use one or more error indicator bits (e.g., color bits) in the WQE to inform a downstream queue (e.g., a downstream pipeline) that the upstream queue/pipeline detected a failed DMA operation. The downstream queue can then perform error handling where it reclaims the resources allocated for the WQE (such as an intermediate buffer).