SCALABLE ARCHITECTURE FOR CONFIGURABLE DYNAMIC ERROR CORRECTION CODING (ECC) MEMORY
卷宗概要
发明人
Sateeshkumar INJARAPU; Amit DUGGAL; Manish Kumar SAXENA; Nitin JAISWAL; Ishwarya ARUMUGAM
IPC 分类
CPC 分类
Aspects of the disclosure are directed to dynamic error correction coding (ECC) disable control. In accordance with one aspect, the disclosure includes assigning each of a plurality of control status registers (CSRs) to each of a plurality of memory groups referenced by a group index to an indicator for error correction coding (ECC) disablement; and performing a dynamic ECC disablement for a plurality of data words for writing to one of the plurality of memory groups according to the indicator in an assigned each of the plurality of CSRs.
原文（中文）
Aspects of the disclosure are directed to dynamic error correction coding (ECC) disable control. In accordance with one aspect, the disclosure includes assigning each of a plurality of control status registers (CSRs) to each of a plurality of memory groups referenced by a group index to an indicator for error correction coding (ECC) disablement; and performing a dynamic ECC disablement for a plurality of data words for writing to one of the plurality of memory groups according to the indicator in an assigned each of the plurality of CSRs.