HARDWARE BASED ARCHITECTURE STATE SAVE AND RESTORE FOR PROCESSING ELEMENTS
卷宗概要
发明人
Akshay DUA; Vinay PATEL; Jae Gon LEE; Nitin MAKHIJA; Mohsen NAJAFI YAZDI; Ayush SINGH; Jihoon JEONG; Sai Akshit Kumar GAMPA; Durga Ganesh CHIMIRALA; Vishal Srinivasan IYER
IPC 分类
CPC 分类
Certain aspects of the present disclosure provide techniques for hardware-based saving and restoring of architecture state information for processing elements (PEs). According to certain aspects, one or more circuit elements trigger saving of architecture state information of at least one processing element (PE) to multiple memories prior to the at least one PE transitioning from a first state to a second state, wherein the architecture state information comprises information associated with different hierarchical levels and trigger restoration of the architecture state information from the multiple memories to the at least one PE prior to the at least one PE transitioning from the second state to the first state.
原文（中文）
Certain aspects of the present disclosure provide techniques for hardware-based saving and restoring of architecture state information for processing elements (PEs). According to certain aspects, one or more circuit elements trigger saving of architecture state information of at least one processing element (PE) to multiple memories prior to the at least one PE transitioning from a first state to a second state, wherein the architecture state information comprises information associated with different hierarchical levels and trigger restoration of the architecture state information from the multiple memories to the at least one PE prior to the at least one PE transitioning from the second state to the first state.