HARDWARE BASED ARCHITECTURE STATE SAVE AND RESTORE FOR PROCESSING ELEMENTS
卷宗概要
发明人
Akshay DUA; Vinay PATEL; Jae Gon LEE; Nitin MAKHIJA; Mohsen NAJAFI YAZDI; Ayush SINGH; Jihoon JEONG; Sai Akshit Kumar GAMPA; Durga Ganesh CHIMIRALA; Vishal Srinivasan IYER
IPC 分类
CPC 分类
Certain aspects of the present disclosure provide techniques for hardware-based saving and restoring of architecture state information for processing elements (PEs). According to certain aspects, the techniques involve triggering, via at least a first circuit element, saving of architecture state information of at least one processing element (PE) to at least one memory prior to the at least one PE transitioning from a first state to a second state; re-routing, via at least a second circuit element, requests to access the state registers to the architecture state RAM, while the at least one PE is in the second state; and triggering, via the first circuit element, restoration of the architecture state information from the at least one memory to the at least one PE prior to the at least one PE transitioning from the second state to the first state.
原文（中文）
Certain aspects of the present disclosure provide techniques for hardware-based saving and restoring of architecture state information for processing elements (PEs). According to certain aspects, the techniques involve triggering, via at least a first circuit element, saving of architecture state information of at least one processing element (PE) to at least one memory prior to the at least one PE transitioning from a first state to a second state; re-routing, via at least a second circuit element, requests to access the state registers to the architecture state RAM, while the at least one PE is in the second state; and triggering, via the first circuit element, restoration of the architecture state information from the at least one memory to the at least one PE prior to the at least one PE transitioning from the second state to the first state.