Memory Bit Correction Via Bit Addressing

原文（中文）

Systems and methods to address and correct individual bits within a data word in memory are disclosed. A data word may correspond to a set of additional bits. Logic in a memory controller may be configured to write a code into the additional bits in the event that a bit within the data word is slow to erase or slow to program. A subsequent read operation may then read the data word as well as the additional bits and correct the particular bit in accordance with the code stored to the additional bits.