Balanced Latency Stacked Cache
卷宗概要
发明人
Carl Dean Dietz
IPC 分类
CPC 分类
In accordance with described techniques for balanced latency stacked cache, a stacked cache system includes a first cache die and at least a second cache die in a stacked orientation with the first cache die. The stacked cache system includes cache control circuitry that is centrally located in the stacked cache system. The stacked cache system also includes connection vias configured vertically in a center of the stacked cache system as interconnected inputs and outputs of the first cache die and the second cache die.
原文(中文)
In accordance with described techniques for balanced latency stacked cache, a stacked cache system includes a first cache die and at least a second cache die in a stacked orientation with the first cache die. The stacked cache system includes cache control circuitry that is centrally located in the stacked cache system. The stacked cache system also includes connection vias configured vertically in a center of the stacked cache system as interconnected inputs and outputs of the first cache die and the second cache die.