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Balanced Latency Stacked Cache

发明专利审中
20权利要求 · 3 独立
§ Ⅰ

卷宗概要

发明人

Carl Dean Dietz

IPC 分类

G6F 12/895G6F 12/897G6F 13/16

CPC 分类

G6F12/895G6F12/897G6F13/161

In accordance with described techniques for balanced latency stacked cache, a stacked cache system includes a first cache die and at least a second cache die in a stacked orientation with the first cache die. The stacked cache system includes cache control circuitry that is centrally located in the stacked cache system. The stacked cache system also includes connection vias configured vertically in a center of the stacked cache system as interconnected inputs and outputs of the first cache die and the second cache die.

原文(中文)

In accordance with described techniques for balanced latency stacked cache, a stacked cache system includes a first cache die and at least a second cache die in a stacked orientation with the first cache die. The stacked cache system includes cache control circuitry that is centrally located in the stacked cache system. The stacked cache system also includes connection vias configured vertically in a center of the stacked cache system as interconnected inputs and outputs of the first cache die and the second cache die.