DESIGN TOOL FOR GENERATION OF A NETWORK-ON-CHIP (NOC) INCLUDING INSERTION OF ADAPTERS IN A PATH

原文（中文）

A design tool is disclosed for generation and synthesis of the network, such as a network-on-chip (NoC). The design tool starts with a deadlock free network design and makes changes or transforms the design to generate a desired NoC, including addressing paths that cross clock domain boundaries or have timing violations. The design tool considers intermediate and proximal regions during the insertion process of distance links, which eliminates distance violations resulting from clock and timing domain traversal by a path.