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SEMICONDUCTOR PACKAGE HAVING TWO-DIMENSIONAL INPUT AND OUTPUT DEVICE

发明专利审中
20权利要求 · 3 独立
§ Ⅰ

卷宗概要

发明人

Kyungsoo KIM; Kyenhee LEE

IPC 分类

H1L 23/498H1L 23/H1L 23/48H1L 23/538H1L 25/7

CPC 分类

H1L23/49816H1L23/481H1L23/49844H1L23/5384H1L24/5H1L24/16H1L25/7H1L2224/401H1L2224/5025H1L2224/16146H1L2924/15311

A semiconductor package is provided. The semiconductor package includes: a first semiconductor chip including a first bonding structure; a first front-end level layer including a first integrated circuit device; a first sub-back-end level layer including a plurality of first metal wire layers, an input and output device level layer including a two-dimensional input and output device, and a second sub-back-end level layer including a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device. The semiconductor package also includes a second semiconductor chip including a bonding structure that is bonded to the first bonding structure; a second front-end level layer including a second integrated circuit device, and a second back-end level layer including a plurality of third metal wire layers electrically connected to the second integrated circuit device.

原文(中文)

A semiconductor package is provided. The semiconductor package includes: a first semiconductor chip including a first bonding structure; a first front-end level layer including a first integrated circuit device; a first sub-back-end level layer including a plurality of first metal wire layers, an input and output device level layer including a two-dimensional input and output device, and a second sub-back-end level layer including a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device. The semiconductor package also includes a second semiconductor chip including a bonding structure that is bonded to the first bonding structure; a second front-end level layer including a second integrated circuit device, and a second back-end level layer including a plurality of third metal wire layers electrically connected to the second integrated circuit device.