METHOD FOR FORMING A TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS

原文（中文）

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a flip-flop having a gated input circuit and a transmission gate. The first time delay circuit is configured to receive a first clock signal and to output a second clock signal. The second time delay circuit is configured to receive the second clock signal and to output a third clock signal. The transmission gate is controlled with the first clock signal and the second clock signal. The gated input circuit is controlled by the third clock signal. The first time delay circuit includes a first gate via-connector in direct contact with a first gate-conductor which intersects a first-type active region structure in a first area. The second time delay circuit includes a second gate via-connector in direct contact with a second gate-conductor which intersects a second-type active region structure in a second area.