SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
卷宗概要
申请人
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.; NATIONAL TAIWAN UNIVERSITY
发明人
Ching-Wang YAO; Hsin-Cheng LIN; Tsai-Yu CHUNG; Tao CHOU; Chee-Wee LIU
IPC 分类
CPC 分类
A method includes forming a first bottom-tier pull-up transistor and a second bottom-tier pull-up transistor over a substrate, wherein the first and second bottom-tier pull-up transistors are comprised in a static random access memory (SRAM) cell; forming a first middle-tier pull-down transistor and a second middle-tier pull-down transistor over the first and second bottom-tier pull-up transistors, wherein the first and second middle-tier pull-down transistors are comprised in the SRAM cell; forming a first top-tier pass-gate transistor, a second top-tier pass-gate transistor, a third top-tier pass-gate transistor, and a fourth top-tier pass-gate transistor over the first and second middle-tier pull-down transistors, wherein the first, second, third, and fourth top-tier pass-gate transistors are comprised in the SRAM cell.
原文（中文）
A method includes forming a first bottom-tier pull-up transistor and a second bottom-tier pull-up transistor over a substrate, wherein the first and second bottom-tier pull-up transistors are comprised in a static random access memory (SRAM) cell; forming a first middle-tier pull-down transistor and a second middle-tier pull-down transistor over the first and second bottom-tier pull-up transistors, wherein the first and second middle-tier pull-down transistors are comprised in the SRAM cell; forming a first top-tier pass-gate transistor, a second top-tier pass-gate transistor, a third top-tier pass-gate transistor, and a fourth top-tier pass-gate transistor over the first and second middle-tier pull-down transistors, wherein the first, second, third, and fourth top-tier pass-gate transistors are comprised in the SRAM cell.