SEMICONDUCTOR DEVICE INCLUDING A TIERED STRUCTURE HAVING TAPERED FILL STRUCTURES

原文（中文）

Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, a memory device includes a vertically-oriented contact pillar and a tiered structure proximate to the vertically-oriented contact pillar. The tiered structure includes an access line between two insulative layers and insulative fill structure. The insulative fill structure includes a tapered portion that is between the vertically-oriented contact pillar and the access line. The tapered portion may be between facing surfaces of ends of the insulative layers.