APPARATUS AND METHODS FOR REDUCING NEAR-NEAR - FAR-FAR MEMORY CELL RESISTANCE DIFFERENCES IN MEMORY ARRAYS

原文（中文）

An apparatus includes a first memory cell coupled between a first word line and a first bit line and series coupled with a first word line resistance and first bit line resistance, and a second memory cell coupled between a second word line and a second bit line and series coupled with a second word line resistance and second bit line resistance. The first memory cell includes a first hard mask including a first hard mask material having a first resistivity, and the second memory cell includes a second hard mask including a second hard mask material having a second resistivity lower than the first resistivity. The first hard mask is configured to compensate for a difference between a first sum of the first word line resistance and the first bit line resistance and a second sum of the second word line resistance and the second bit line resistance.