THIN FILM TRANSISTORS HAVING MULTI-LAYER CONTACT METALLIZATION
卷宗概要
发明人
Shailesh Kumar MADISETTI; Suraj MATHEW; Huiying LIU; Xiaoye QIN; Vladimir NIKITIN; Moshe DOLEJSI; Jannatul Ferdous MOUSUMI; Gregory J. GEORGE; Abhishek Anil SHARMA; Van H. LE; Travis W. LAJOIE
IPC 分类
CPC 分类
Thin film transistors are described. An integrated circuit structure includes a gate electrode. A gate dielectric layer is on the gate electrode. A channel material layer is on the gate dielectric layer. A dielectric layer is over the channel material layer. Source or drain contacts are on the channel material layer. Each of the source or drain contacts includes a semiconductor material layer, a conductive liner on and within the semiconductor material layer, and a conductive fill on the conductive liner, where one, two or all three of the semiconductor material layer, the conductive liner, or the conductive fill has an uppermost surface at a same level as an uppermost surface of the dielectric layer.
原文（中文）
Thin film transistors are described. An integrated circuit structure includes a gate electrode. A gate dielectric layer is on the gate electrode. A channel material layer is on the gate dielectric layer. A dielectric layer is over the channel material layer. Source or drain contacts are on the channel material layer. Each of the source or drain contacts includes a semiconductor material layer, a conductive liner on and within the semiconductor material layer, and a conductive fill on the conductive liner, where one, two or all three of the semiconductor material layer, the conductive liner, or the conductive fill has an uppermost surface at a same level as an uppermost surface of the dielectric layer.