STRAIN ENGINEERING USING GATE CUTS

原文（中文）

Techniques are provided herein to form semiconductor devices that include one or more gate cuts having materials that impose either a compressive or tensile stress on the adjacent semiconductor devices to improve performance. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The gate cut is confined within the gate trench. A first gate cut is arranged between adjacent NMOS devices and includes a dielectric material that imposes a tensile stress on the NMOS devices, and a second gate cut is arranged between adjacent PMOS devices and includes a dielectric material that imposes a compressive stress on the PMOS devices.