INTEGRATED CIRCUIT STRUCTURES HAVING STRESS-INDUCING GATE CUT PLUGS
卷宗概要
发明人
Tao CHU; Guowei XU; Robin CHAO; Feng ZHANG; Ting-Hsiang HUNG; Chia-Ching LIN; Yang ZHANG; Kan ZHANG; Chun Wing YEUNG; Minwoo JANG; Yanbin LUO; Chung-Hsun LIN; Anand S. MURTHY; Paul A. PACKAN
IPC 分类
CPC 分类
Integrated circuit structures having stress-inducing gate cut plugs are described. For example, a structure includes a first vertical stack of horizontal nanowires or fin over a first sub-fin. A first gate structure is over the first vertical stack of horizontal nanowires or fin. A second vertical stack of horizontal nanowires or fin is over a second sub-fin. A second gate structure is over the second fin. A gate cut separates a first gate electrode of the first gate structure from a second gate electrode of the second gate structure. A gate cut fill structure is in the gate cut, the gate cut fill structure including a first dielectric material portion in contact with the first gate electrode, a conductive via portion, and a second dielectric material portion in contact with the second gate electrode. The conductive via portion separates the first dielectric material portion from the second dielectric material portion.
原文（中文）
Integrated circuit structures having stress-inducing gate cut plugs are described. For example, a structure includes a first vertical stack of horizontal nanowires or fin over a first sub-fin. A first gate structure is over the first vertical stack of horizontal nanowires or fin. A second vertical stack of horizontal nanowires or fin is over a second sub-fin. A second gate structure is over the second fin. A gate cut separates a first gate electrode of the first gate structure from a second gate electrode of the second gate structure. A gate cut fill structure is in the gate cut, the gate cut fill structure including a first dielectric material portion in contact with the first gate electrode, a conductive via portion, and a second dielectric material portion in contact with the second gate electrode. The conductive via portion separates the first dielectric material portion from the second dielectric material portion.