CNIPA.AI
返回搜索
档案

SEMICONDUCTOR DEVICES

发明专利审中
1浏览
20权利要求 · 3 独立
§ Ⅰ

卷宗概要

发明人

Sanghyun Sung; Jinwoo Han

IPC 分类

H10D 64/27H10B 12/H10D 64/66

CPC 分类

H10D64/518H10B12/482H10D64/514H10D64/666H10D64/669H10B12/5

A semiconductor device includes channel structures extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, intersecting the first horizontal direction, bit lines extending in a vertical direction with each of the bit lines contacting a first end of a respective channel structure, a gate electrode extending in the second horizontal direction and surrounding the channel structures, gate dielectric layers with each gate dielectric layer between a respective channel structure and the gate electrode, and information storage structures extending in the vertical direction with each information storage structure contacting a second end of a respective channel structure that is opposite the first end of the respective channel structure. The gate electrode includes first conductive patterns with each first conductive pattern surrounding a respective channel structure, and a second conductive pattern surrounding the first conductive patterns.

原文(中文)

A semiconductor device includes channel structures extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, intersecting the first horizontal direction, bit lines extending in a vertical direction with each of the bit lines contacting a first end of a respective channel structure, a gate electrode extending in the second horizontal direction and surrounding the channel structures, gate dielectric layers with each gate dielectric layer between a respective channel structure and the gate electrode, and information storage structures extending in the vertical direction with each information storage structure contacting a second end of a respective channel structure that is opposite the first end of the respective channel structure. The gate electrode includes first conductive patterns with each first conductive pattern surrounding a respective channel structure, and a second conductive pattern surrounding the first conductive patterns.