SELECTIVE PROCESS FOR SIMULTANEOUS PFET EPI HARDMASK AND NFET PARTIAL BOTTOM DIELECTRIC ISOLATION LAYER FORMATION

原文（中文）

Embodiments described herein generally relate to methods of forming hardmask and bottom dielectric isolation layers in vertical trench structures. A method of forming a gate-all-around field-effect transistor includes depositing a conformal oxide layer on a channel surface and a bottom surface of vertical structures of a substrate, the vertical structures including an NMOS portion having NMOS vertical structures defining NMOS contact trenches and a PMOS portion having PMOS structures defining PMOS contact trenches having a PMOS source/drain layer deposited therein. The method further includes selectively etching the conformal oxide layer at the bottom surface of the vertical structures, inhibiting the conformal oxide layer, selectively depositing a nitride layer at the bottom surface of the vertical structures, etching the conformal oxide layer to expose the channel surface of the vertical structures, and depositing an NMOS source/drain layer on the bottom surface of the NMOS contact trenches.