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L-SHAPED STACKED FIELD EFFECT TRANSISTOR ISOLATED WITH TOP AND BOTTOM GATES

发明专利审中
20权利要求 · 3 独立
§ Ⅰ

卷宗概要

发明人

Chen Zhang; Shahrukh Khan; Ruilong Xie; Shay Reboh

IPC 分类

H1L 27/92H1L 21/822H1L 21/8238H1L 29/6H1L 29/423H1L 29/66H1L 29/775H1L 29/786

CPC 分类

H10D84/856H10D30/14H10D30/43H10D30/6735H10D30/6757H10D62/121H10D64/17H10D84/167H10D84/17H10D84/188H10D84/38H10D88/1

A semiconductor has a gate line with a gate line opening flanked by a pair of source/drains. In the gate line opening are a bottom transistor and a top transistor. The bottom transistor includes a bottom set of nanosheets wrapped by a bottom workfunction material while the top transistor includes a top set of nanosheets wrapped by a top workfunction material. A dielectric structure separates the bottom transistor and the top transistor. The dielectric structure includes a middle dielectric portion (which can be L-shaped), a first plug laterally contacting a first side of the middle dielectric portion and a second plug laterally contacting a second side of the middle dielectric portion.

原文(中文)

A semiconductor has a gate line with a gate line opening flanked by a pair of source/drains. In the gate line opening are a bottom transistor and a top transistor. The bottom transistor includes a bottom set of nanosheets wrapped by a bottom workfunction material while the top transistor includes a top set of nanosheets wrapped by a top workfunction material. A dielectric structure separates the bottom transistor and the top transistor. The dielectric structure includes a middle dielectric portion (which can be L-shaped), a first plug laterally contacting a first side of the middle dielectric portion and a second plug laterally contacting a second side of the middle dielectric portion.