Controlled Transition Between Configuration Mode and User to Reduce Current-Resistance Voltage Drop
卷宗概要
发明人
Atul Maheshwari; Ankireddy Nalamalpu; Mahesh A. Iyer; Mahesh K. Kumashikar
IPC 分类
CPC 分类
Systems or methods of the present disclosure may provide for gradually adjusting a frequency of a clock signal. When transitioning from a configuration mode to a user mode, a clock of an integrated circuit (e.g., a field-programmable gate array or FPGA) may quickly (e.g., instantaneously) switch from a low configuration mode frequency to a high user mode frequency. This rapid increase in clock frequency may cause an inrush current and corresponding current-resistance voltage (IR) drop. To reduce or avoid the inrush current and IR drop, a frequency of the clock may be gradually ramped up from the configuration mode frequency to the user mode frequency.
原文（中文）
Systems or methods of the present disclosure may provide for gradually adjusting a frequency of a clock signal. When transitioning from a configuration mode to a user mode, a clock of an integrated circuit (e.g., a field-programmable gate array or FPGA) may quickly (e.g., instantaneously) switch from a low configuration mode frequency to a high user mode frequency. This rapid increase in clock frequency may cause an inrush current and corresponding current-resistance voltage (IR) drop. To reduce or avoid the inrush current and IR drop, a frequency of the clock may be gradually ramped up from the configuration mode frequency to the user mode frequency.