REDUNDANT ARRAY PARITY INFORMATION STORAGE
卷宗概要
发明人
Pranav Tharanath; Amiya Banerjee; Sriraman Sridharan
IPC 分类
CPC 分类
Methods, systems, and devices for redundant array parity information storage are described. A memory system may store parity information associated with data in one or more latches associated with one or more planes before writing the data from the latches to the one or more planes. The parity information may be transferred from the latches to the one or more planes. The memory system may temporarily transfer the parity information from the latches to the planes before completing the write operation in response to initiating a write operation that uses more of the latches, and may transfer the parity information back to the latches after the write operation is completed. The memory system may store, retrieve, and transfer the parity information to or from the latches according to an interleaving scheme associated with different write operations of the memory system.
原文（中文）
Methods, systems, and devices for redundant array parity information storage are described. A memory system may store parity information associated with data in one or more latches associated with one or more planes before writing the data from the latches to the one or more planes. The parity information may be transferred from the latches to the one or more planes. The memory system may temporarily transfer the parity information from the latches to the planes before completing the write operation in response to initiating a write operation that uses more of the latches, and may transfer the parity information back to the latches after the write operation is completed. The memory system may store, retrieve, and transfer the parity information to or from the latches according to an interleaving scheme associated with different write operations of the memory system.