CONTROL LOGIC IN A MEMORY DEVICE FOR GENERATING INTERNAL COMMANDS

原文（中文）

An apparatus comprising an array of memory cells, a register coupled to the array of memory cells, and control logic coupled to the register and the array of memory cells. The control logic is configured to issue an internal command in response to a memory controller receiving an external command, generate an address corresponding to the internal command, provide the internal command to a row decoder and a column decoder, and instruct a processing unit (PU) to perform multiply-accumulate (MAC) operations on received data.