ADDRESS TRANSLATION FOR ACCELERATOR-TRIGGERED MEMORY ACCESS REQUESTS

原文（中文）

An apparatus comprises processing circuitry to execute instructions; memory management circuitry associated with the processing circuitry, to perform address translation in response to memory access instructions executed by the processing circuitry; and accelerator control interface circuitry to exchange control signals with at least one hardware accelerator configurable, based on instructions executed by the processing circuitry, to perform a delegated task. The memory management circuitry is configured to maintain a plurality of active translation contexts of a given translation regime, each active translation context being defined by context information stored in a corresponding set of context control registers; and the apparatus further comprises context fault generating circuitry to generate a context fault indication in response to an accelerator-triggered memory access request from a given hardware accelerator and associated with a translation context other than one of the plurality of active translation contexts.