MEMORY DEVICE AND OPERATING METHOD THEREOF
卷宗概要
申请人
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.; NATIONAL TSING HUA UNIVERSITY
发明人
Yi-Lun LU; Tai-Hao WEN; Yu-Chen CHANG; Win-San KHWA; Jui-Jen WU; Meng-Fan CHANG
IPC 分类
CPC 分类
A memory device includes a memory array configured to store weight data; a control logic configured to transmit input data to activate different numbers of multiple word lines in each of multiple cycles of multiply-and-accumulate (MAC) operations on the weight data and the input data; and multiple read circuits coupled to the memory array through multiple bit lines, and configured to generate, in response to a control signal, multiple read voltages based on multiple reference voltages in the cycles of MAC operations to the bit lines. The reference voltages are different from each other.
原文（中文）
A memory device includes a memory array configured to store weight data; a control logic configured to transmit input data to activate different numbers of multiple word lines in each of multiple cycles of multiply-and-accumulate (MAC) operations on the weight data and the input data; and multiple read circuits coupled to the memory array through multiple bit lines, and configured to generate, in response to a control signal, multiple read voltages based on multiple reference voltages in the cycles of MAC operations to the bit lines. The reference voltages are different from each other.