PROCESSING FOR PROCESSORS PERFORMING TASKS INVOLVING LOOPS

原文（中文）

Embodiments of the technology described herein include hardware of a processor configured to decrease the number of pipeline flushes caused by loop instructions by extracting data regarding the loop during the instruction fetch stage of the instruction cycle of the processor and/or updating the data as determined during the execution stage of the instruction cycle of the processor. In this regard, the control unit of the processor can direct the instruction fetch unit of the processor to fetch instructions of the loops based on the number of iterations of the loop as stored in a register associated with the instruction fetch stage of the processor. In this manner, certain computing devices employing embodiments of the technology described herein decrease the number of pipeline flushes, thereby increasing computational efficiency and hardware lifespan compared to using conventional technology.