Processor Employing Instruction That Performs A Bitwise Majority Vote Operation

原文（中文）

A system includes a feedback control loop signal path. Circuitry of the signal path includes three processors. Each processor (“slice”) includes an ADC, a digital signal processor (DSP), and a DAC. The DSPs of the three slices execute identical programs of instructions, and are clocked in unison so that at any given time they are executing the same instruction. The DSP of the slice executes an instruction that performs a “register bitwise majority vote” (RMAJ) operation. The instruction identifies a register of the slice, and the data content of this register is output via a bus to the two other slices. The DSP performs a bitwise majority vote on: 1) the data content of the register, 2) the data content of the corresponding register in each of the other two slices. The result of the bitwise majority vote is written into the register of the slice.