REGISTER FILE PACKING
卷宗概要
发明人
Steven Gregory Flolid; John Kalamatianos
IPC 分类
CPC 分类
A central processing unit (CPU) is disclosed. The CPU includes: a physical register file (PRF) including a plurality of physical registers; an instruction queue configured to store an instruction identifying an opcode, a source operand register, and a destination operand register; and an allocator, configured to allocate a first physical register to the destination operand register, where the first physical register has a first changeable bit size corresponding with a result bit size of the destination operand register.
原文（中文）
A central processing unit (CPU) is disclosed. The CPU includes: a physical register file (PRF) including a plurality of physical registers; an instruction queue configured to store an instruction identifying an opcode, a source operand register, and a destination operand register; and an allocator, configured to allocate a first physical register to the destination operand register, where the first physical register has a first changeable bit size corresponding with a result bit size of the destination operand register.