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ERROR HANDLING MANAGEMENT CORE

发明专利审中
2浏览
20权利要求 · 3 独立
§ Ⅰ

卷宗概要

发明人

Carlos Vallin; Vilas Sridharan; Magiting Talisayon; Kasir Asad Watkins

IPC 分类

G6F 11/7

CPC 分类

G6F11/787G6F11/721

The disclosed device includes a processor core and a management core. The management core can intercept error interrupts indicating errors for the processor core. The management core can process the error while the processor core continues operations, and can also cloak the error from an operating system. The management core can also provide the errors to a baseboard controller for storing in a non-volatile memory. Various other methods, systems, and computer-readable media are also disclosed.

原文(中文)

The disclosed device includes a processor core and a management core. The management core can intercept error interrupts indicating errors for the processor core. The management core can process the error while the processor core continues operations, and can also cloak the error from an operating system. The management core can also provide the errors to a baseboard controller for storing in a non-volatile memory. Various other methods, systems, and computer-readable media are also disclosed.