SIGNAL PROCESSING APPARATUS AND METHOD
卷宗概要
发明人
Atsufumi SHIBAYAMA
IPC 分类
CPC 分类
A signal processing apparatus includes a storage processing part to perform processing on data represented in a second representation format, wherein the second representation format, while for a non-negative value identical to two's complement representation, for a negative value, has a representation format where (D−N−1) bits of the data of D-bits in the two's complement representation are bit-wise inverted, the (D−N−1) bits located between MSB and N consecutive lower bits including LSB, the storage processing part including a normalization circuit with a maximum exponent calculation circuit and a shift circuit to normalize a plurality of pieces of data represented in the second representation format for each block.
原文（中文）
A signal processing apparatus includes a storage processing part to perform processing on data represented in a second representation format, wherein the second representation format, while for a non-negative value identical to two's complement representation, for a negative value, has a representation format where (D−N−1) bits of the data of D-bits in the two's complement representation are bit-wise inverted, the (D−N−1) bits located between MSB and N consecutive lower bits including LSB, the storage processing part including a normalization circuit with a maximum exponent calculation circuit and a shift circuit to normalize a plurality of pieces of data represented in the second representation format for each block.