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SELECTIVE TRACING BASED ON ISOLATION IN SOFTWARE BASED DEVICES

发明专利审中
11浏览
20权利要求 · 3 独立
§ Ⅰ

卷宗概要

发明人

Ayushi Agarwal; Aditya Vikram Chopra; Juhee Mala

IPC 分类

G6F 21/55G6F 11/362G6F 21/54

CPC 分类

G6F21/556G6F11/3636G6F21/54

An apparatus and method are disclosed for a System on Chip (SoC) which includes a central interconnect fabric connected between a plurality of initiators and targets, where the central interconnect includes one or more debug trace probes for connection to a debugger, where each debug trace probe is connected with debug firewall control logic configured to allow a data trace packet from a first cohort to be traced out to the debug trace probe only if the data trace packet includes a CID value associated with the first cohort that matches a CCID value associated with a configuring cohort which configures the debug trace probe, and where the debug firewall control logic includes a secure trace enable multiplexer connected to packet capture control logic which is configured to output a packet capture enable signal indicating whether the data trace packet is a secure packet or unsecure packet.

原文(中文)

An apparatus and method are disclosed for a System on Chip (SoC) which includes a central interconnect fabric connected between a plurality of initiators and targets, where the central interconnect includes one or more debug trace probes for connection to a debugger, where each debug trace probe is connected with debug firewall control logic configured to allow a data trace packet from a first cohort to be traced out to the debug trace probe only if the data trace packet includes a CID value associated with the first cohort that matches a CCID value associated with a configuring cohort which configures the debug trace probe, and where the debug firewall control logic includes a secure trace enable multiplexer connected to packet capture control logic which is configured to output a packet capture enable signal indicating whether the data trace packet is a secure packet or unsecure packet.