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LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS

发明专利审中
24权利要求 · 1 独立
§ Ⅰ

卷宗概要

发明人

Mou-Shiung Lin; Jin-Yuan Lee

IPC 分类

G6F 30/34G5B 19/42G6F 3/6G11C 7/10G11C 11/412H1L 25/16H1L 25/18H3K 19/177H3K 19/1776H10B 20/H10B 41/35

CPC 分类

G6F30/34G5B19/423G6F3/605G6F3/659G11C7/1012G11C7/1045G11C7/106G11C11/412H1L25/16H1L25/18H3K19/177H3K19/1776H10B20/65H10B41/35G5B2219/15057H1L2224/4105H1L2224/12105H1L2224/18H1L2224/24137H1L2224/32225H1L2224/73204H1L2224/73267H1L2924/18162

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

原文(中文)

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.