MEMORY DEVICE
卷宗概要
发明人
Tsuneo UENAKA; Tomoya INDEN; Shigehiro YAMAKITA
IPC 分类
CPC 分类
According to one embodiment, a memory device includes a first silicon substrate, a second silicon substrate, and a memory cell array. A first CMOS circuit is formed on the first silicon substrate. The second silicon substrate is provided above the first silicon substrate in a stacking direction. A second CMOS circuit is formed on the second silicon substrate. The memory cell array is provided above the second silicon substrate in the stacking direction. The memory cell array is connected to the first CMOS circuit and the second CMOS circuit and includes a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate.
原文（中文）
According to one embodiment, a memory device includes a first silicon substrate, a second silicon substrate, and a memory cell array. A first CMOS circuit is formed on the first silicon substrate. The second silicon substrate is provided above the first silicon substrate in a stacking direction. A second CMOS circuit is formed on the second silicon substrate. The memory cell array is provided above the second silicon substrate in the stacking direction. The memory cell array is connected to the first CMOS circuit and the second CMOS circuit and includes a plurality of memory cells arranged in the stacking direction of the first silicon substrate and the second silicon substrate.