MEMORY WITH REDUNDANT READ OPTIMIZATION
卷宗概要
发明人
Asheesh Singh BAGHEL; Amit DUGGAL; Sateeshkumar INJARAPU
IPC 分类
CPC 分类
A memory is provided with a redundant read logic circuit that detects whether a current read operation should proceed as a redundant or non-redundant read operation. In a redundant read operation, the memory does not assert a word line voltage nor does it enable any sense amplifiers. The data for a redundant read operation is thus not provided by the memory but instead is retrieved from a global input/output (GIO) memory circuit such as a GIO latch.
原文（中文）
A memory is provided with a redundant read logic circuit that detects whether a current read operation should proceed as a redundant or non-redundant read operation. In a redundant read operation, the memory does not assert a word line voltage nor does it enable any sense amplifiers. The data for a redundant read operation is thus not provided by the memory but instead is retrieved from a global input/output (GIO) memory circuit such as a GIO latch.