MEMORY CIRCUIT WITH BIT LINE CLAMPS
卷宗概要
申请人
Xilinx, Inc.
发明人
Kumar Rahul; Santosh Yachareni; Md Hussain; Tabrez Alam; Nui Chong
IPC 分类
CPC 分类
A memory circuit is disclosed. The memory circuit includes a plurality of bit lines; a plurality of memory cells arranged in columns, each memory cell connected to a pair of bit lines; and a plurality of clamp circuits, each including a first clamp and logic circuit connected to a first bit line and a second clamp and logic circuit connected to a second bit line, where the first clamp and logic circuit is configured to selectively clamp the first bit line in response to the memory circuit operating in a particular mode, and where the second clamp and logic circuit is configured to selectively clamp the second bit line in response to the memory circuit operating in the particular mode.
原文（中文）
A memory circuit is disclosed. The memory circuit includes a plurality of bit lines; a plurality of memory cells arranged in columns, each memory cell connected to a pair of bit lines; and a plurality of clamp circuits, each including a first clamp and logic circuit connected to a first bit line and a second clamp and logic circuit connected to a second bit line, where the first clamp and logic circuit is configured to selectively clamp the first bit line in response to the memory circuit operating in a particular mode, and where the second clamp and logic circuit is configured to selectively clamp the second bit line in response to the memory circuit operating in the particular mode.