CIRCUIT FOR MULTIPORT REGISTER FILE
卷宗概要
发明人
Rahul MATHUR; Andy Wangkun CHEN; Yew Keong CHONG; Parveen KUMAR
IPC 分类
CPC 分类
Various implementations described herein are related to a read multiplexer circuit for a multiport register file, comprising: an input stage coupled to an array of storage nodes, each storage node coupled to drive an output of a respective bitcell; a read stage comprising control logic dividing the array of storage nodes into one or more sets and first circuitry that provides a first read word line to a first storage node of a first set for reading data from the first storage node and a second read word line to a second storage node of the first set for reading data from the second storage node; and a first latch stage comprising second circuitry that provides a third read word line to the first and second storage node of the first set to latch the read from one of the first and second storage nodes.
原文（中文）
Various implementations described herein are related to a read multiplexer circuit for a multiport register file, comprising: an input stage coupled to an array of storage nodes, each storage node coupled to drive an output of a respective bitcell; a read stage comprising control logic dividing the array of storage nodes into one or more sets and first circuitry that provides a first read word line to a first storage node of a first set for reading data from the first storage node and a second read word line to a second storage node of the first set for reading data from the second storage node; and a first latch stage comprising second circuitry that provides a third read word line to the first and second storage node of the first set to latch the read from one of the first and second storage nodes.