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LEVEL-BASED PROGRAMMING WITH MULTIPLE ANALOG PROGRAM VERIFY OPERATIONS BETWEEN PROGRAMMING PULSES

发明专利审中
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21权利要求 · 3 独立
§ Ⅰ

卷宗概要

发明人

Huai-Yuan Tseng; Eric Nien-Heng Lee; Akira Goda; Yoshihiko Kamata; Koichi Kawai

IPC 分类

G11C 16/34G11C 16/4G11C 16/10

CPC 分类

G11C16/3459G11C16/10G11C16/483

A method includes causing, in between applying programming pulses to selectively store data to multiple voltage levels of a plurality of memory cells, a second occurrence of a first analog verify operation to be performed on a first set of memory cells to identify one or more memory cells of a first subset of the first set of memory cells. The first subset of memory cells are those that failed the first analog verify operation and the one or more memory cells twice failed the first analog verify operation. A first occurrence of a second analog verify operation is performed at a second set of memory cells to identify a second subset of the second set of memory cells that failed the second analog verify operation.

原文(中文)

A method includes causing, in between applying programming pulses to selectively store data to multiple voltage levels of a plurality of memory cells, a second occurrence of a first analog verify operation to be performed on a first set of memory cells to identify one or more memory cells of a first subset of the first set of memory cells. The first subset of memory cells are those that failed the first analog verify operation and the one or more memory cells twice failed the first analog verify operation. A first occurrence of a second analog verify operation is performed at a second set of memory cells to identify a second subset of the second set of memory cells that failed the second analog verify operation.