POWER SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
卷宗概要
申请人
TONG HSING ELECTRONIC INDUSTRIES, LTD.
发明人
Yan-Wei Chen; Chih-Jen Su
IPC 分类
CPC 分类
A power semiconductor package includes a substrate; a chip affixed to the substrate via a dual-layer sintered silver bonding structure; and an epoxy molding compound that at least encapsulates the chip and a portion of the dual-layer sintered silver bonding structure. The dual-layer sintered silver bonding structure includes a first sintered silver layer positioned on the substrate, and a second sintered silver layer positioned on the first sintered silver layer, with the chip located on the second sintered silver layer. The first sintered silver layer has a porosity of less than 5%, and the second sintered silver layer has a Young's modulus of less than 20 GPa.
原文（中文）
A power semiconductor package includes a substrate; a chip affixed to the substrate via a dual-layer sintered silver bonding structure; and an epoxy molding compound that at least encapsulates the chip and a portion of the dual-layer sintered silver bonding structure. The dual-layer sintered silver bonding structure includes a first sintered silver layer positioned on the substrate, and a second sintered silver layer positioned on the first sintered silver layer, with the chip located on the second sintered silver layer. The first sintered silver layer has a porosity of less than 5%, and the second sintered silver layer has a Young's modulus of less than 20 GPa.