WAFER-SCALE SYSTEM-IN-PACKAGE STRUCTURE AND FORMING METHOD THEREOF
卷宗概要
申请人
JCET Microelectronics (Jiangyin) Co. Ltd
发明人
Danfeng YANG; Songhua XU; Ming HE; Pingping LI; Yao LI; Yaojian LIN
IPC 分类
CPC 分类
A wafer-scale system-in-package structure and a forming method thereof are disclosed. The package structure includes: a substrate, where the substrate includes an upper surface and a lower surface that are opposite to each other; a first molding layer that wraps the plurality of semiconductor chips and the upper surface of the substrate; external protrusions on the lower surface of the substrate; and a second molding layer that wraps side surfaces of the plurality of external protrusions and the lower surface of the substrate, where a thickness of the second molding layer is less than a thickness of the first molding layer, and at least one of the coefficient of thermal expansion or Young's modulus of the second molding layer is equal to or higher than that of the first molding layer. In this way, warpage of the system-in-package structure can be effectively controlled.
原文（中文）
A wafer-scale system-in-package structure and a forming method thereof are disclosed. The package structure includes: a substrate, where the substrate includes an upper surface and a lower surface that are opposite to each other; a first molding layer that wraps the plurality of semiconductor chips and the upper surface of the substrate; external protrusions on the lower surface of the substrate; and a second molding layer that wraps side surfaces of the plurality of external protrusions and the lower surface of the substrate, where a thickness of the second molding layer is less than a thickness of the first molding layer, and at least one of the coefficient of thermal expansion or Young's modulus of the second molding layer is equal to or higher than that of the first molding layer. In this way, warpage of the system-in-package structure can be effectively controlled.