SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC LAYER AND PARAELECTRIC LAYER

原文（中文）

Provided is a semiconductor device including a substrate, a stacked structure including a plurality of gate electrodes and a plurality of interlayer insulating layers, and a plurality of channel structures penetrating the stacked structure. Each of the plurality of channel structures includes a channel poly layer, a crystalline layer including hafnium (Hf) or zirconium (Zr), an electron trap layer, and a plurality of gate insulating layers positioned between the electron trap layer and the plurality of gate electrodes at a height corresponding to the plurality of gate electrodes. The crystalline layer includes a plurality of ferroelectric layers positioned at a height corresponding to the plurality of gate electrodes, and a plurality of paraelectric layers positioned at a height corresponding to the plurality of interlayer insulating layers. The plurality of ferroelectric layers and the plurality of paraelectric layers have different crystal structures while containing the same material.