VERTICALLY STACKED MEMORY ARRAYS CORRESPONDING TO RESPECTIVE SINGLE DOPANT TYPES

原文（中文）

Techniques and mechanisms for an integrated circuit (IC) die structure to comprise heterogeneous active layers which are stacked with each other to form structures of respective memory arrays. In an embodiment, an IC die structure comprises first metal oxide semiconductor field effect transistors (MOSFETs) of a first active layer, and second MOSFETs of a second active layer which is vertically stacked with the first active layer. A first memory array comprises the first MOSFETs, and a second memory array comprises the second MOSFETs. The first memory array comprises a four transistor (4T) static random access memory (SRAM) cell, each transistor of which corresponds to a first dopant type. The second memory array comprises a second memory cell, each transistor of which corresponds to a second dopant type. In another embodiment, a cell density of the first memory array is substantially less than that of the second memory array.