Three-dimensional memory array, memory and electronic equipment

The invention provides a preparation method of a three-dimensional memory array, a memory and electronic equipment. Relates to the technical field of semiconductor storage. Each memory cell in the three-dimensional memory array comprises a first transistor and a second transistor, the second transistor serving as a read transistor can adopt a double-gate structure, one gate is electrically connected with the first transistor serving as a write transistor, and the other gate can be electrically connected with a read word line. One of the source and the drain of the second transistor is grounded. Therefore, when the memory unit performs read operation, the voltage drop phenomenon on the read word line can be weakened; besides, in the process structure of the memory cell, each film layer structure of the first transistor and each film layer structure of the second transistor are integrated in the at least four stacked insulating dielectric layers, and when the process structure is prepared, three-dimensional stacking of the memory array can be realized, so that the memory capacity is improved.