Thermally assisted SOT-MRAM device, memory array and memory chip

The invention relates to a heat-assisted SOT-MRAM device, a storage array and a storage chip. The device comprises a top electrode, at least one magnetic tunnel junction, a write current channel layer, a heat insulation layer and a substrate, the magnetic tunnel junction comprises a reference layer, a tunneling layer and a magnetic free layer which are stacked in sequence, the write current channel layer is located above the substrate, the magnetic tunnel junction is located above the write current channel layer, and the reference layer, the tunneling layer and the magnetic free layer are stacked in sequence. The top electrode is located above the magnetic tunnel junction, and the thermal insulation layer is located at least one of the following parts: the lower part of the write current channel layer and the part between the write current channel layer and the substrate; and the write current channel layer is above the write current channel layer and is at least located at two sides of the magnetic tunnel junction. The write current and power consumption of the SOT-MRAM can be reduced, and the reduction of the write current can reduce the area of a write transistor and increase the storage density.