Adapter plate and preparation method thereof, chip packaging structure and electronic equipment

The embodiment of the invention provides an adapter plate and a preparation method thereof, a chip packaging structure and electronic equipment, relates to the technical field of semiconductors, and is used for reducing parasitic capacitance of metal wiring in the adapter plate. The adapter plate comprises a substrate and at least one rewiring layer stacked on the substrate. The rewiring layer comprises at least one first dielectric layer, at least one second dielectric layer, a metal wire and a first via hole, wherein the first dielectric layer and the second dielectric layer are alternately arranged, and the metal wire and the first via hole are electrically connected. Wherein the metal wiring is located in the first dielectric layer, and the first via hole is located in the second dielectric layer. And at least one gap is formed in the at least one second dielectric layer.