元の名称記録: Arista Networks, Inc.

A network device may include data plane processing circuitry and memory circuitry accessible by the data plane processing circuitry to perform traffic processing operations. The memory circuitry may sometimes experience memory errors such as bit flips. One or more processors on the network device may access the memory circuitry, in parallel with the data plane processing circuitry accessing the memory circuitry, to detect and correct these memory errors more quickly, thereby reducing disruptions to traffic processing operations caused by memory errors.

A network device may include memory circuitry such as a ternary content addressable memory (TCAM) for implementing a memory profile having qualifiers based on which flow entries are defined for network traffic matching. To facilitate the implementation of a custom memory profile on the TCAM, the controller may obtain support information for the TCAM, may obtain user configuration information indicative of a network policy, and may identify qualifiers for a memory profile customized based on the TCAM support information and the user configuration information. The network device may receive the identified qualifiers from the controller and configure the custom memory profile on the TCAM.

A network device uses prefix compression to program routes in a forwarding information base (FIB) in a longest prefix match (LPM) table or an exact match (EM) table. The network device compresses routes of a certain prefix length in the FIB into a single entry in the EM table. For a compressed prefix that does not correspond to a route in the FIB (hole), the network device associates the hole with a special value rather than the prefix of a covering route. When the network device receives a packet that matches a hole, the lookup performed on the exact match table results in the special value. In response, the network device uses the result of the lookup performed on the LPM table to determine how to forward the packet.

A network device may include control plane processing circuitry configured to obtain packet-processing-element-specific policer profiles for applying a traffic policy to a logical interface formed from physical interfaces coupled to different packet processing elements. Each of the packet processing elements may be configured to process matching network traffic using its policer configured based on the corresponding packet-processing-element-specific policer profile. The packet processing elements may thereby collectively apply the traffic policy in the intended manner.

A networking device controls transmission to an egress port with a virtual output queue using credits received from an egress scheduler. Credits may be requested at various rates based on the size of the virtual output queue. To optimize latency and prevent unused credits, the thresholds for changing the requested credit rates is determined based on the credit rate and the round-trip time from the virtual input queue to the egress scheduler. This ensures that when incoming data to the virtual output queue ends, the scheduler does not issue credits faster than the virtual output queue can signal changes to the effective credit rates.

Electrical paths between ports (interfaces) of a network device are provided using an arrangement of interconnected Layer 1 (L1) crossbar switches in the network device. The network device includes internal data tables, e.g., a reachability table and a plurality of Layer 1 forwarding tables. These data tables are generated from a description of the crossbar chips in the network device. Heuristics are used to define one or more paths through the crossbar switches to connect between user-specified ports on the network device. The heuristics can select paths between ports based on criteria such a lowest latency, path stability (i.e., minimizing disruption to existing paths), and the like. The heuristic can be driven by a user who specifies via a CLI one or more crossbar switches on the path between the specified ports.