一种快速同步的时钟同步电路及其控制方法
本发明公开了一种快速同步的时钟同步电路,包含频率检测模块、时钟选择模块、第一时钟同步模块、第二时钟同步模块和第三时钟同步模块,频率检测模块检测外部时钟信号CLK_EX,当外部时钟信号CLK_EX为空时,使能信号EN_H=0,当外部时钟信号CLK_EX不为空时,使能信号EN_H=1,开始时钟同步。本发明构成简单,面积小,实施成本低;内部时钟与外部时钟的切换时间短,可快速完成时钟同步;采用“闩锁”逻辑,避免外部毛刺抖动影响内部时钟输出,具有良好的抗干扰性能。
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